It is well known that dimensions of transistors in integrated circuits (ICs) are shrinking with each new generation of fabrication technology, as articulated in Moore's Law. Source and drain elements of MOS transistors are shrinking in both lateral and vertical directions, requiring tighter control over dopant distributions to maintain transistor performance parameters such as on-state drive current and off-state leakage current. Source and drain elements of n-channel MOS transistors typically include two sub-elements: a shallow, lightly doped region, commonly known as the n-type lightly doped drain (NLDD) closest to the MOS transistor channel region, and a deeper, heavily doped region commonly known as the n-type source/drain (NSD), which is typically laterally separated from the MOS transistor channel region. The NLDD and NSD sub-elements are formed separately. NLDD and NSD sub-elements of n-channel MOS transistors are formed by ion implanting n-type dopants into a p-type region of the surface of a silicon wafer. In addition, p-type dopants are typically ion implanted at an angle during the NLDD formation process, commonly known as a halo implant, to reduce the short channel effect. Commonly used n-type dopants are arsenic (As) and phosphorus (P). Phosphorus has a disadvantage for use in the NLDD and NSD, which arises from the high diffusivity of P atoms in silicon. After the n-type dopants are ion implanted into the NLDD or NSD, the wafer is annealed at high temperature to repair the silicon crystal lattice damage done by the ion implantation process. During the anneal, P atoms diffuse away from the implanted NLDD or NSD region into the transistor body region, further degrading on-state drive current and off-state leakage current. A common p-type dopant for halo implants is boron (B), which has the same disadvantage of high diffusivity as phosphorus. Carbon may be implanted into the NLDD to reduce the diffusion of P and B atoms during an anneal. However, carbon atoms in the NLDD space charge region contribute to diode leakage current, known as gated diode leakage (GDL). Arsenic is also commonly ion implanted into NLDD and NSD regions for n-channel MOS transistors. However, arsenic has a disadvantage of causing damage to the silicon crystal lattice during ion implantation, which is correlated with formation of metal silicide defects, known as pipes, which cause undesirable high off-state leakage current, and failures in static random access memory (SRAM) bits. Typical NLDD and NSD fabrication processes balance doses of phosphorus and arsenic to minimize the total impact to transistor on-state drive current and off-state leakage current. Lighter As or P doses in NLDD and NSD implants to reduce the deleterious effects produce undesirable higher series resistance in the transistor.
It is common for ICs to have two types of NMOS transistors: the second type has a higher threshold than the first type. High threshold NMOS is typically formed by the same process sequence as core NMOS, with the exception that high threshold NMOS receives an extra dose of p-type dopants in the region immediately under a gate to increase the threshold voltage. High threshold NMOS has lower off-state leakage current than core NMOS. GDL from the reverse biased junction between the drain and the p-type channel region is a dominant source of off-state leakage current in high threshold NMOS transistors, which is undesirable for IC performance.